ISO/IEC 18372:2004
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ISO/IEC 18372:2004
38668

Status : Published (Under review)

This standard was last reviewed and confirmed in 2018. Therefore this version remains current.
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Format Language
std 1 216 PDF on CD
  • CHF216
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The electronic version of this International Standard can be downloaded from the ISO/IEC Information Technology Task Force (ITTF) web site

Abstract

The RapidIO architecture was developed to address the need for a high-performance low pin count packet-switched system level interconnect to be used in a variety of applications as an open standard. The architecture is targeted toward networking, telecom, and high performance embedded applications. It is intended primarily as an intra-system interface, allowing chip-to-chip and board-toboard communications at Gigabyte per second performance levels. It provides a rich variety of features including high data bandwidth, low-latency capability and support for high-performance I/O devices, as well as providing globally shared memory, message passing, and software managed programming models.

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General information

  •  : Published
     : 2004-12
    : International Standard confirmed [90.93]
  •  : 1
     : 405
  • ISO/IEC JTC 1/SC 25
    35.100.30 
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